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Freescale Semiconductor Technical Data
Document Number: MC34700 Rev. 5.0, 10/2009
9.0 to 18 V, Quad Output, Integrated MOSFET Power Supply
The 34700 is a compact, high-efficiency power supply with on-chip power MOSFETs that features three step-down switching regulators and one low dropout linear regulator. The switching regulators utilize voltage mode control with external compensation, allowing flexibility in optimizing the performance of the 34700 for a given application. The 34700 is ideal for space constrained applications where multiple power rails are required and simplicity of design and implementation of the power supply is necessary. Over-voltage, under-voltage, over-current, and over-temperature protection features ensure robust and reliable operation. Fixed switching frequency, internal soft-start, and internal power MOSFETs enable rapid power supply design and development. The 34700 is well suited for power supply designs in wide variety of applications, including set top boxes, cable modems, laser printers, fax machines, point-of-sale terminals, small appliances, telecom line cards, and DVD players. Typical Applications: * Set Top Boxes and Receivers * Cable Modems * Networking Cards * Telecom Line Cards
MC34700
POWER SUPPLY 98ASA10800D 32-Pin QFN, 5 x 5mm ORDERING INFORMATION
Device MC34700EP/R2 Temperature Range (TA) -40C to 85C Package 32 QFN
Features
* Three switching regulators: 2 synchronous and 1 nonsynchronous * One low dropout linear regulator * Output current capability: * 1.5 A continuous on channel 1 * 1.25 A continuous on channels 2 and 3 * 400 mA continuous on channel 4 * Internal power MOSFETs on all channels * Voltage feed-forward on channel 1 * 1.5% Output voltage accuracy on all channels * Cycle-by-cycle current limit and short-circuit protection * Fixed 800 kHz switching frequency * Internal soft-start * Over-voltage, under-voltage and over-temperature protection * Open-drain power-good output signal * Separate active-high enable input for each channel * Pb-free packaging designated by suffix code EP
VIN1
9 V - 18 V VIN VDDI VGREG PGOOD VIN1
MC34700
VOUT1 VIN2 VIN3 BST1 SW1 COMP1 FB1 BST2 SW2 COMP2
VOUT1 2.0 - 5.25 V, 1.5 A
VOUT2 0.7 - 3.6 V, 1.25 A
Enable 1 Enable 2 Enable 3 Enable 4
EN1 EN1 EN1 EN_LDO
FB2 BST3 SW3 COMP3
VOUT3 0.7 - 3.6 V, 1.25 A
AGND GND2 GND3
FB3 LDO_VIN LDO
VOUT4 0.7 - 3.6 V, 0.4 A
LDO_FB
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2009. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VOUT1
Ramp Generator PGOOD Supervisory Logic Channel 1 Regulator Control
Feed Forward
Bootstrap Circuit
BST1 VIN1
Gate Drive SW1
EN1 EN2 EN3 EN4 EN_LDO
Main System Control
COMP1 FB1
Thermal Monitoring Current Monitoring System Reset Ramp Generator Bootstrap Circuit BST2 VIN2
Bandgap Reference
Channel 2 Regulator Control 0.7V Internal Reference
Gate Drive
SW2
GND2 COMP2
VDDI FB2 POR VDDI Internal Regulator
VGREG
Bootstrap Circuit Oscillator Ramp Generator
BST3 VIN3
VIN
VG Regulator
Channel 3 Regulator Control
Gate Drive
SW3
LDO_VIN
GND3 COMP3
LDO LDO_FB
FB3
AGND
Figure 2. 34700 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Table 1. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. This is a stress only rating and operation at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Ratings ELECTRICAL RATINGS Input Voltages Input Voltage Input DC/DC1 Voltage, IVIN = 0 Input DC/DC2, 3, and LDO Voltage Switch Node Voltages Switch Node DC/DC1 Switch Node DC/DC2, DC/DC3 Bootstrap Voltages Bootstrap DC/DC1 Bootstrap DC/DC2, DC/DC3 Bootstrap Voltage Referenced to Switch Node Voltage Compensation (COMP1, 2, and 3), Feedback (FB1, FB2, FB3, LDO_FB), VDDI All Other Pins (EN1, 2, 3, EN_LDO, PGOOD, VGREG, LDO, VOUT1) ESD Voltage
(1)
Symbol
Value
Unit
V VIN VIN1 VIN2, VIN3, VINLDO VSW1 VSW2, VSW3 VBST1 VBST2, VBST3 VBST - VSW VESD + 2000 -0.3 to 20 -0.3 to 20 -0.3 to 7 V -0.3 to 20 -0.3 to 7 V -0.3 to 25 -0.3 to 14 -0.3 to 7 -0.3 to 3 -0.3 to 7 V V V
Human Body Model (HBM) All Pins THERMAL RATINGS Operating Temperature Ambient Junction Peak Package Temperature During Reflow Storage Temperature THERMAL RESISTANCE Thermal Resistance (2) Junction-to-Case Junction-to-Ambient Power Dissipation TA = 25C TA = 70C TA = 85C TJC TJA PD
(2), (3)
C TA TJ TPPRT TSTRG -40 to +85 -40 to +125 300 -40 to +150 C C
C/W 6.7 37 W 2.5 1.3 1.0
Notes 1. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ). 2. 3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
Table 2. Electrical Characteristics Characteristics noted under conditions 9.0 V VIN 18 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic POWER SUPPLY VIN Voltage Maximum Minimum Standby Current Operating Current Internal Supply Voltage POWER-ON RESET VGREG Rising Threshold Voltage VGREG Falling Threshold Voltage VGREG Hysteresis Voltage VGREG LINEAR REGULATOR On Resistance Output Voltage Maximum Input dV/dT BIAS VOLTAGES VGREG Decoupling VDDI Decoupling ENABLE Output Enable Logic High Threshold Voltage Output Enable Logic Low Threshold Voltage EN Input Resistance to Ground Delay from Enable to Soft Start DC1 Delay from Enable to Soft Start DC2, DC3 REFERENCE DC/DC 1, 2, 3 Reference Voltage LDO Reference Voltage OSCILLATOR Switching Frequency SOFT-START Soft-start Duration DC1, 2, 3 Soft-start Duration LDO tSS_BUCKREG tSS_LDO 2.5 0.3 3.5 0.5 4.5 0.7 ms ms fSW 760 800 840 kHz VREF1,2,3 VREF_LDO 0.690 0.690 0.700 0.700 0.710 0.710 V V VEN1,2,3 VEN_LDO VEN1,2,3 VEN_LDO REN_IN tDELAY1 tDELAY2,3 1.5 1.0 160 M ms ms 0.78 0.61 V V VGREG = 5.0 V VDDI = 2.5 V CVGREG CVDDI 1.0 1.0 F F VIN1 = VIN IVGREG = 80 mA RVGREGIN VVGREG VIN_dV/dT 4.75 30 5.25 10 5.5 V V/s VVGREG_RISING VVGREG_FALLING VVGREG_HYS 3.5 3.0 0.2 4.0 3.4 0.55 4.5 4.0 1.0 V V V VEN1 = VEN2 = VEN3 = VEN_LDO = 0 V VEN1 = VEN2 = VEN3 = VEN_LDO = 5.0 V, VVIN = 9.0 V, Load = 0 A ISDB IIN VDDI VIN 2.3 18 9.0 8.95 15.4 2.5 15 2.7 mA mA V V Test Conditions Symbol Min Typ Max Unit
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
Table 2. Electrical Characteristics (continued) Characteristics noted under conditions 9.0 V VIN 18 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic RAMP GENERATORS Ramp Amplitude (DC/DC1) VFF Gain (DC/DC1) Ramp Amplitude (DC/DC2,3) VFF Gain (DC/DC2,3) Ramp Bottom (DC/DC1,2,3) Min Duty Cycle (DC/DC1) Max Duty Cycle (DC/DC1) Min Duty Cycle (DC/DC2,3) Max Duty Cycle (DC/DC2,3) POWER-GOOD O V Threshold, all regulators UV Threshold, all regulators PGOOD Output Low Level PGOOD Reset Delay PGOOD Glitch Rejection BUCK CONVERTER 1 Maximum VIN1 Input Voltage Minimum VIN1 Input Voltage Maximum Output Voltage Minimum Output Voltage Maximum Output Current Total System Accuracy Peak Short-circuit Current Limit High Side On Resistance Equivalent Dropout Resistance Error Amplifier DC Gain Error Amplifier Unity-gain Bandwidth Error Amplifier Slew Rate @ 15 pF Current Limit Timer Current Limit Retry Timeout Period VIN1 = 5.5 V, VOUT = 3.3 V, ILOAD = 2.0 A VIN = 9.0V VIN = 9.0V VIN1_MAX VIN1_MIN VDC1VOUTMAX VDC1VOUTMIN IOUTDC1MAX VOUT1 ISHORT1 RDS(ON)_HS RDO AEA GBW SR tLIM1 tTIMEOUT1 -1.5 2.5 18 9.0 5.25 2.0 1.5 150 183 110 4.0 1.8 10 100 1.5 4.5 V V V V A % A m m dB MHz V/s ms ms Percentage of setpoint Percentage of setpoint ISINK = 6.0 mA OV_TH UV_TH VOL_PGOOD tPG-RESET tPG-FILTER 92 0.4 100 10 108 % % V s s ILOAD1 = 0 A ILOAD1 = 0 A ILOAD1 = 0 A ILOAD1 = 0 A VFF_GAIN2 x PVIN2, PVIN2 = 6.0 V VFF_GAIN1 x PVIN1, PVIN1 = 18 V VRAMP_AMP1 VFF_GAIN1 VRAMP_AMP2,3 VFF_GAIN2,3 VRAMP_OFFSET D1 D1 D2,3 D2,3 68.4 83.6 1.0 0.055 1.25 0.208 0.2 0 16 0 VP-P V/V VP-P V/V V % % % % Test Conditions Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
Table 2. Electrical Characteristics (continued) Characteristics noted under conditions 9.0 V VIN 18 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic BUCK CONVERTER 2 Maximum VIN2 Input Voltage Minimum VIN2 Input Voltage Maximum Output Voltage Minimum Output Voltage Maximum Output Current Total System Accuracy Peak Short-circuit Current Limit High Side On Resistance Low Side On Resistance Equivalent Dropout Resistance VIN2 = 1.7 V, VOUT = 1.25 V, ILOAD = 1.25 A SW2 Leakage Current Error Amplifier DC Gain Error Amplifier Unity Gain Bandwidth Error Amplifier Slew Rate Current Limit Timer Current Limit Retry Timeout Period BUCK CONVERTER 3 Maximum VIN3 Input Voltage Minimum VIN3 Input Voltage Maximum Output Voltage Minimum Output Voltage Maximum Output Current Total System Accuracy Peak Short-circuit Current Limit High Side On Resistance Low Side On Resistance Equivalent Dropout Resistance VIN2 = 1.7 V, VOUT = 1.25 V, ILOAD = 1.25 A SW3 Leakage Current Error Amplifier DC Gain Error Amplifier Unity Gain Bandwidth Error Amplifier Slew Rate Current Limit Timer Current Limit Retry Timeout Period VIN = 12 V, VIN3 = 0 V, EN3 = 0 V ISW3 AEA GBW SR tLIM3 tTIMEOUT3 400 110 4.0 1.8 10 100 A dB MHz V/s ms ms VIN3_MAX VIN3_MIN VDC3VOUTMAX VDC2VOUTMIN IOUTDC3MAX VOUT3 ISHORT3 RDS(ON)_HS RDS(ON)_LS RDO -1.5 2.0 6.0 1.5 3.6 0.7 1.25 160 140 150 1.5 4.5 V V V V A % A m m m VIN = 12 V, VIN2 = 0 V, EN2 = 0 V ISW2 AEA GBW SR tLIM2 tTIMEOUT2 400 110 4.0 1.8 10 100 A dB MHz V/s ms ms VIN = 9.0 V VIN = 9.0 V VIN2_MAX VIN2_MIN VDC2VOUTMAX VDC2VOUTMIN IOUTDC2MAX VOUT2 ISHORT2 RDS(ON)_HS RDS(ON)_LS RDO -1.5 2.0 6.0 1.5 3.6 0.7 1.25 175 150 150 1.5 4.5 V V V V A % A m m m Test Conditions Symbol Min Typ Max Unit
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
Table 2. Electrical Characteristics (continued) Characteristics noted under conditions 9.0 V VIN 18 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic LINEAR REGULATOR Maximum LDO Input Voltage Minimum LDO Input Voltage Maximum LDO Output Voltage Minimum LDO Output Voltage Maximum LDO Output Current Total System Accuracy Maximum Dropout Voltage LDO Power Dissipation Maximum Output Current Minimum Output Current Required Output Decoupling ILDO = 400 mA VINLDO VINLDO VLDO VLDO ILDO VLDO VDROP PDISS_LDO ISHORT_LDO ISHORT_LDO CLDO CESR Current Limit Retry Timeout Period THERMAL SHUTDOWN Maximum Thermal Shutdown Threshold Typical Thermal Shutdown Threshold Minimum Thermal Shutdown Threshold Thermal Shutdown Hysteresis TSD_MAX TSD TSD_MIN TSD_HYS 160 140 120 25 C C C C tTIMEOUT_LDO -1.5 6.0 1.5 3.6 0.7 400 250 375 1100 500 10 20 100 1.5 V V V V mA % mV mW mA mA F m ms Test Conditions Symbol Min Typ Max Unit
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PIN CONNECTIONS FUNCTIONAL PIN DESCRIPTIONS
PIN CONNECTIONS
PGOOD
27
32
31
30
29
28
26
VIN1 SW1 SW1 BST1 GND2 SW2 VIN2 BST2
VGREG
25 24 23 22
COMP1
VOUT1
AGND
VDDI
VIN1
FB1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VIN LDO_VIN LDO LDO_FB GND3 SW3 VIN3 BST3
TRANSPARENT TOP VIEW
PIN 33
21 20 19 18 17
FB2
COMP2
FB3
Figure 3. 34700 Pin Connections
FUNCTIONAL PIN DESCRIPTIONS
Table 3. 34700 Pin Definitions
Pin 1,32 2,3 4 5 6 7 8 9 10 11 12
Name VIN1 SW1 BST1 GND2 SW2 VIN2 BST2 COMP2 FB2 EN1 EN2
Pin Description Buck regulator #1's power input voltage. VIN1 is connected to the drain of the DC/DC #1's high side MOSFET. Local bypass capacitors are recommended. Buck regulator #1's switching node. SW1 is connected to the source of the high side MOSFET. Connect this pin to the cathode of the catch diode and the output inductor. Buck regulator #1's bootstrap capacitor input. Connect a capacitor between the BST1 and SW1 pin of DC/DC #1 to enhance the gate of the high side MOSFET during switching. Buck regulator #2's power ground. GND2 is connected to the source of DC/DC #2's low side MOSFET. Connect this pin to the DC/DC #2's power return path. Buck regulator #2's switching node. SW2 is connected to source of the high side and the drain of the low side MOSFET. Connect this pin to the output inductor. Buck regulator #2's power input voltage. VIN2 is connected to the drain of the DC/DC #2's high side MOSFET. Local bypass capacitors are recommended. Buck regulator #2's bootstrap capacitor input. Connect a capacitor between the BST2 and SW2 pin of DC/DC #2 to enhance the gate of the high side MOSFET during switching. Buck regulator #2's compensation output. COMP2 is connected to DC/DC #2's error amplifier's output. Connect the required external compensation network between the COMP2 pin and the FB2 pin. DC/DC #2's error amplifier inverting input. Connect the required compensation network and feedback network to this terminal as appropriate. This input enables buck regulator #1. Asserting EN1 high turns on DC/DC #1. The internal control logic remains active as long as VIN is present. This input enables buck regulator #2. Asserting EN2 high turns on DC/DC #2. The internal control logic remains active as long as VIN is present.
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EN_LDO
COMP3
EN1
EN2
EN3
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS FUNCTIONAL PIN DESCRIPTIONS
Table 3. 34700 Pin Definitions (continued)
Pin 13 14 15 16 17 18 19 20 21 22 23 24 25
Name EN3 EN_LDO FB3
COMP3 BST3
Pin Description This input enables buck regulator #3. Asserting EN3 high turns on DC/DC #3. The internal control logic remains active as long as VIN is present. This input enables the LDO. Asserting EN_LDO high turns on the LDO. The internal control logic remains active as long as VIN is present. DC/DC #3's error amplifier inverting input. Connect the required compensation network and feedback network to this terminal as appropriate. Buck regulator #3's compensation output. COMP3 is connected to DC/DC #3's error amplifier's output. Connect the required external compensation network between the COMP3 pin and the FB3 pin. Buck regulator #3's bootstrap capacitor input. Connect a capacitor between the BST3 and SW3 pin of DC/DC #3 to enhance the gate of the high side MOSFET during switching. Buck regulator #3's power input voltage. VIN3 is connected to the drain of the DC/DC #3's high side MOSFET. Local bypass capacitors are recommended. Buck regulator #3's switching node. SW3 is connected to source of the high side and the drain of the low side MOSFET. Connect this pin to the output inductor. Buck regulator #3's power ground. GND3 is connected to the source of DC/DC #3's low side MOSFET. Connect this pin to the DC/DC #3's power return path. LDO error amplifier inverting input. Connect the appropriate output voltage feedback resistor divider to this pin. LDO regulator output. Connect this pin to the feedback resistor divider and output capacitor. LDO's power input voltage. LDO_VIN is connected to the drain of the linear regulator's pass device. Local bypass capacitors are recommended. IC supply voltage input. This pin should be de-coupled from the buck regulator's power input voltages (VIN1, VIN2, VIN3). Filtering is required for proper device operation. This is the output of an internal linear regulator which is used to supply the gate drivers. The VGREG linear regulator is driven from the input supply voltage VIN, and it's output is also used to drive the gates of the low side MOSFETs of regulators DC/DC #2 and DC/DC #3, as well as the LDO. Connect this pin to a low ESR, 1.0 F bypass capacitor. Internal regulator output used to supply the internal logic and analog blocks. VDDI is driven from the gate drive supply voltage, VGREG. Connect this pin to a 1.0 F, low ESR decoupling filter capacitor. Status signal used to indicate that all the regulators' output voltages are good. Upon a fault occurrence, this output signal goes low. PGOOD is an open drain output, and must be pulled up by an external resistor to a supply voltage suitable for I/O. Analog ground of the IC. Internal analog and logic signals are referenced to this pin. DC/DC #1's shunt input. VOUT1 is connected to a discharge MOSFET. This MOSFET is used to discharge the output of DC/DC1 when there is a fault condition, such as thermal shutdown or a short circuit. It is also used to provide a pre-load to maintain a minimum duty. Connect this pin to the output of DC/DC #1. DC/DC #1's error amplifier inverting input. Connect the required compensation network and feedback network to this terminal as appropriate. Buck regulator #1's compensation output. COMP1 is connected to DC/DC #1's error amplifier's output. Connect the required external compensation network between the COMP1 pin and the FB1 pin. Thermal pad for heat transfer. Connect the thermal pad to the analog ground.
VIN3 SW3 GND3 LDO_FB LDO LDO_VIN VIN VGREG
26 27
VDDI PGOOD
28 29
AGND VOUT1
30 31 33
FB1 COMP1 AGND
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PIN CONNECTIONS ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
CH1 Efficiency (3.36VOUT)
0.9
0.7
LDO Efficiency (0.89VOUT)
0.8
0.65
0.7
LDO Efficiency
CH1 Efficiency
9VIN 0.6 11VIN 13VIN 15VIN 17VIN 18VIN 0.4
0.6 1.5VIN 0.55 1.6VIN 1.7VIN 1.8VIN 0.5
0.5
0.3
0.45
0.2 0 0.2 0.4 0.6 0.8 CH1 Iout (A) 1 1.2 1.4 1.6
0.4 0 0.1 0.2 0.3 0.4 0.5 LDO Iout (A)
Figure 1. Typical CH1 Efficiency
Figure 4. Typical LDO Efficiency
CH2 Efficiency (2.49VOUT)
0.96 0.94 0.92 0.9 CH2 Efficiency
Magnitude (dB) 40 60
CH1 Loop Response
180
135
Phase
20
90
0.86 0.84 0.82 0.8
4.5VIN 5.5VIN 6VIN
0
0
-45 -20 -90 -40
0.78 0.76 0 0.2 0.4 0.6 0.8 1 1.2 1.4 CH2 Iout (A)
-60 100.0E+0 1.0E+3 10.0E+3 Frequency (Hz) 100.0E+3
-135
-180 1.0E+6
Figure 2. Typical CH2 Efficiency
Figure 5. CH1 Loop Response - Application Example
CH3 Efficiency (1.28VOUT)
0.96 0.94 0.92 0.9 CH3 Efficiency
20 Magnitude (dB) 40 60
CH2 Loop Response
180
Phase
135
90
0.88 0.86 0.84 0.82 0.8
4VIN 5VIN 6VIN
0
0
-45 -20 -90 -40
0.78 0.76 0 0.2 0.4 0.6 0.8 1 1.2 1.4 CH3 Iout (A)
-60 100.0E+0 1.0E+3 10.0E+3 Frequency (Hz) 100.0E+3
-135
-180 1.0E+6
Figure 3. Typical CH3 Efficiency
Figure 6. CH2 Loop Response - Application Example
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Analog Integrated Circuit Device Data Freescale Semiconductor
Phase (deg)
3VIN
45
Phase (deg)
0.88
3.5VIN
45
PIN CONNECTIONS ELECTRICAL PERFORMANCE CURVES
CH3 Loop Response
60 180
Phase
40
135
EN3
90 20 Magnitude (dB) 45
0
0
COMP3 VOUT3 SW3
-45 -20 -90 -40 -135
-60 100.0E+0 1.0E+3 10.0E+3 Frequency (Hz) 100.0E+3
-180 1.0E+6
3.4 VIN3, 1.28 VOUT1@ 1.25 A
Figure 7. CH3 Loop Response - Application Example
Figure 10. EN CH3 Start-up
EN1 COMP1
EN_LDO VOUT3
VOUT1 SW1
VOUT_LDO SW3
12 VIN1, 3.4 VOUT1@ 1.5 A
1.28 VIN_LDO, 0.9 VOUT_LDO@ 0.4 A
Figure 8. EN CH1 Start-up
Figure 11. EN LDO Start-up
VOUT1 EN2 VIN COMP2 VOUT2 SW2 SW1
3.4 VIN2, 2.5 VOUT1@ 1.25 A
12 VIN1, 3.4 VOUT1@ 0 A
Figure 9. EN CH2 Start-up
Figure 12. CH1 Short-circuit Response
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PIN CONNECTIONS ELECTRICAL PERFORMANCE CURVES
VIN2 VOUT2
IOUT2-1.0A/div
VOUT2 COMP2
SW2
SW2
5 VIN2, 2.47 VOUT2@ 0 A
5 VIN2, 2.47 VOUT2@ 0 A, 0 to 1.25 A transient
Figure 13. CH2 Short-circuit Response
Figure 16. CH2 Transient Response
VIN3 IOUT3-1.0A/div
VOUT3 VOUT3 COMP3
SW3
SW3
5 VIN3, 1.28 VOUT3@ 0 A
5 VIN3, 1.28 VOUT3@ 0 A, 0 to 1.25 A transient
Figure 14. CH3 Short-circuit Response
Figure 17. CH3 Transient Response
VOUT1 IOUT1 1.0 A/div COMP1
IOUT_LDO3-250mA/div
VOUT_LDO
VIN_LDO
SW1
12 VIN1, 3.38 VOUT1@ 0 A, 0 to 2 A transient
1.5 VIN_LDO, 0.9 VOUT_LDO@ 0 A, 0 to 400mA transient
Figure 15. CH1 Transient Response
Figure 18. LDO Transient Response
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION INITIALIZATION
FUNCTIONAL DEVICE OPERATION
INITIALIZATION
When power is first applied to the 34700, the internal regulators and bias circuits need to be up and stable before the power on reset (POR) signal is released. The POR waits until the gate drive regulator's voltage, VGREG, has reached about 4.0 V before it allows the rest of the internal blocks to be enabled. Each regulator has an independent enable pin. This allows the user to program the power up sequence to suit the application. As each regulator is turned on, it will execute a soft start ramp of the output voltage. This is done to prevent the output voltage from overshooting the regulation point. Without a soft start ramp, the output voltage will ramp up faster than the control loop can typically respond, resulting in overshoot. As a result, the soft start periods for the switching regulators are longer (3.5 ms) than for the linear regulator (0.5 ms). The soft start is active each time the regulator is enabled, after a fault retry, or when the IC power is recycled. After a successful start-up sequence, where all the regulators are enabled, no faults have occurred, and the output voltage is in regulation, the power good signal goes open drain after a 100 s reset delay. A power good true indicates that all the regulators are functioning in normal operation mode.
OPERATIONAL MODES
Each regulator of the 34700 has three basic modes of operation.
OUTPUT OVER-VOLTAGE
An over-voltage (OV) condition occurs when the output voltage exceeds the over-voltage threshold, OV_TH. This can occur if the regulator's output is shorted to a supply with a higher output voltage. In this case, the power good signal is pulled low, alerting the host that a fault is present, but the regulator remains active. The regulator will continue to try to regulate the output: DC/DC1 will pulse skip; DC/DC2, 3 will go to minimum duty; and the LDO pass device will go high impedance. To avoid false trips of the OV monitor, the power good circuit has a 10 s glitch filter. Once the output voltage falls below the OV threshold and back into regulation, the fault is cleared and the power good signal goes high.
NORMAL MODE
In normal mode, the regulator is fully operational. To be in this mode, the 34700 input supply, VIN, needs to be present and within its operating range. The regulator's power input voltage also needs to be present and in range. The ENABLE pin for the regulator needs to be asserted, and the output voltage needs to be in regulation. No over-current or thermal faults are present in normal mode.
STANDBY MODE
In standby mode, the ENABLE pin for the regulator is held low and the regulator is disabled. VIN needs to be present and within its operating range. The regulator's power input is not needed in this mode, but needs to be present and stable before transitioning to normal mode. No faults are present in standby mode. Note that the standby mode consumes the least amount of power.
OUTPUT UNDER-VOLTAGE
An under-voltage (UV) condition occurs when the output voltage falls below the under-voltage threshold, UV_TH. This can occur if the regulator's output is shorted to ground, overloaded, or the power input voltage has decreased. In this case, the power good signal is pulled low, alerting the host that a fault is present, but the regulator remains active. The regulator will continue to try to regulate the output: DC/DC1, 2, 3 will go to maximum duty or current limit; and the LDO pass device will go to a low resistance. To avoid false trips of the UV monitor, the power good circuit has a 10 s glitch filter. Once the output voltage rises above the UV threshold and back into regulation, the fault is cleared and the power good signal goes high.
FAULT MODE
In fault mode, the output is no longer in regulation, or an over-current or a thermal fault is present. To be in this mode the 34700 input supply, VIN needs to be present and within its operating range. The regulator's power input voltage also needs to be present and in range. However, if the power input is outside the operating range, a regulation fault may occur. The ENABLE pin for the regulator needs to be asserted.
PROTECTION FUNCTIONS
The 34700 monitors the regulators for several fault conditions to protect both the system load and the IC from overstress. The response of the 34700 to a fault condition is described as follows.
CURRENT LIMIT
A current limit condition for the switching regulators' occurs when the peak current in the high side power MOSFET exceeds the current limit threshold. The switch current is monitored using a sense FET and a comparator. The sense FET acts as a current detecting device by sampling a fraction of the current in the power MOSFET. This
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FUNCTIONAL DEVICE OPERATION DESIGN AND COMPONENT GUIDELINES
sampled current is compared to an internal reference to determine if the regulator is exceeding the current limit or not. If the peak switch current reaches the peak current limit threshold (ISHORT), the regulator will start the cycle by cycle current limit operation, the power good signal is pulled low after the 10 s glitch filter, and a 10 ms current limit timer (tLIM) begins. The regulator will stay in this mode of operation until one of the following occur: * The current is reduced back to normal levels before the current limit timer expires and normal operation is resumed. * The current limit timer expires without regaining normal operation, at which time the regulator turns off. The regulator remains off for a 100 ms retry timeout period (tTIMEOUT), after which the regulator will attempt a soft start cycle. * The switch current continues to increase until it exceeds the cycle by cycle current limit by approximately 1.0 A. At this point the regulator shuts down immediately. The regulator remains off for a 100 ms retry timeout period (tTIMEOUT), after which the regulator will attempt a soft start cycle. * The device reaches the thermal shutdown limit (TSD), the regulator turns off.
pulling low. The regulator will stay in this mode of operation until the temperature of the die has decreased by the hysteresis value, and the regulator will attempt a soft start cycle.
POWER SUPPLIES
DC/DC1 This is a non-synchronous switching buck regulator, utilizing a feed-forward voltage mode control, with external compensation. This is the only converter in this IC that will regulate from a wide input supply voltage of 9.0 to 18 V. It is capable of generating a 2.0 to 5.25 V output at 1.5 A. DC/DC2 This is a synchronous switching buck regulator whose input can be fed from DC/DC1, or an external 1.5 to 6.0 V source. It utilizes voltage mode control with external compensation. It is capable of generating a 0.7 to 3.6 V output at 1.25 A. DC/DC3 This buck regulator is identical to DC/DC2. Note that all three switching regulators switch at 800 kHz, and are 120 out of phase to help reduce system noise and input surge currents. LDO This low drop out regulator can feed off of any of the switching regulators or from an external 1.5 to 6.0 V source. The dropout voltage is 250 mV at the rated load. It is capable of generating a 0.7 to 3.6 V output at 400 mA.
THERMAL SHUTDOWN
A thermal limit condition occurs when a power device reaches the thermal shutdown threshold (TSD). The temperature of the power MOSFETs in the switching regulators and the LDO are monitored using a thermal sensing transistor located near the power devices. If the temperature of a switcher or an LDO reaches the thermal shutdown threshold, the switcher or LDO regulator will switch off and the PGOOD output would indicate a fault by
DESIGN AND COMPONENT GUIDELINES INPUT/OUTPUT CONFIGURATION
The 34700 has independent inputs for each regulator. This allows a high degree of flexibility as far as how the IC can be configured. First, consider what supplies are available in the application, and the input voltage range for each regulator. Only Buck Converter 1 has a 9.0 to 18 V input voltage range. All the other regulators have a 1.5 to 6.0 V input voltage range. Next, consider the output voltages and currents required, and how best to match them to the 34700. Buck Converter 1 is capable of 2.0 to 5.25 V at 1.5 A, while Buck Converters 2 and 3 are capable of 0.7 to 3.6 V at 1.25 A each. The LDO is capable of 0.7 to 3.6 V at a 400 mA output. Some sample configurations are show in Figures 19 thru 21. Note that not all combinations are shown, and all the regulators require an input voltage higher than the output voltage.
9.0 to 18 V IN Buck Converter 1 2.0 to 5.25 V OUT 1.5 A MAX
1.5 to 6.0 V IN
Buck Converter 2 Buck Converter 3
0.7 to 3.6 V OUT 1.25 A MAX 0.7 to 3.6 V OUT 1.25 A MAX
1.5 to 6.0 V IN
1.5 to- 6.0 V IN
LDO
0.7 to 3.6 V OUT 400 mA MAX
Figure 19. General Configuration
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FUNCTIONAL DEVICE OPERATION DESIGN AND COMPONENT GUIDELINES
9.0 to 18 V IN
Buck Converter 1
2.0 to 5.25 V OUT
1.5 to 6.0 V IN
Buck Converter 2 Buck Converter 3
0.7 to 3.6 V OUT
0.7 to 3.6 V OUT
When making the power calculations, be sure to include any input currents from regulators that are connected to the converter as part of the output current. For example, the input currents of Buck Converters 2 and 3 should be added to the system load current of Buck Converter 1 shown in Figure 21. After completing the calculations for all the regulators, check to make sure there are no violations of the power budget - input currents exceeding supply current capabilities, or output currents exceeding the regulator's rating.
MINIMUM/MAXIMUM DUTY LIMIT
LDO
Figure 20. Dual Input Supply Configuration
9.0 to 18 V IN
Buck Converter 1
2.0 to 5.25 V OUT
Based on the application specifications, the minimum and maximum duty cycle of the buck converters need to be checked against the limits. For Buck Converter 1, there is a minimum limit of 16% and a maximum limit of 68.4%. For Buck Converters 2 and 3 there is a maximum limit of 83.6%. The duty cycle for a buck converter is calculated using:
Buck Converter 2 Buck Converter 3
0.7 to 3.6 V OUT
D=
VOUT x100% VIN
0.7 to 3.6 V OUT
LDO
This equation works for calculating the minimum duty cycle, however, the above formula does not take into account load currents and losses. A more accurate equation for calculating the maximum duty under load follows:
0.7 to 3.6 V OUT
Figure 21. Single Input Supply Configuration
D MAX =
INPUT/OUTPUT POWER
Based on the application specifications and the regulator's configuration, the input and output power requirements need to be checked. For the LDO, the input and output powers are calculated:
VOUT + (R DO + R DC ) x I OUT x 100% VIN(MIN)
POUT(LDO) = VOUT x I OUT PIN(LDO) = VIN x I IN I IN = I OUT
For the buck converters, the input and output powers are calculated:
Where RDO is the equivalent dropout resistance of the buck converter and RDC is the DC resistance of the inductor. Check to make sure all the buck converters are within the duty cycle limit. Converters, where the calculated maximum duty cycle exceeds the limit, run the risk of dropping out of regulation under load. Conversely, the maximum duty cycle limit can be used to predict the maximum load current that can be drawn without the output dropping out of regulation.
I OUT(MAX)
D MAX x VIN - VOUT 100% = (R DO + R DC )
POUT(BUCK) = VOUT x I OUT PIN(BUCK) = I IN = POUT ( BUCK )
LDO DROPOUT AND POWER DISSIPATION
The input of the LDO needs to exceed the output voltage by a minimum of 250 mV, in order to maintain regulation. If the input voltage falls below the dropout level, the output voltage will also start to fall and begin to track the input voltage down. However, choosing an input voltage that exceeds the output voltage by a large amount is not recommended either. This is due to increased power dissipation. The linear regulators power dissipation is calculated using:
PIN(BUCK) VIN
Where is the estimated efficiency of the buck converters, use 0.85 for the initial estimate.
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FUNCTIONAL DEVICE OPERATION DESIGN AND COMPONENT GUIDELINES
PDISS = (VOUT - VIN ) x I OUT
Since the maximum power dissipation for the LDO is 375 mW, the user can determine what the limits are for the LDO's input voltage.
VOUT + 0.25V VIN VOUT +
0.375 I OUT
CASCADED OPERATION, SEQUENCING, AND LEAKAGE
When the 34700 is configured for cascaded operation, where the output of one regulator powers the input of another regulator (see Figure 21), the startup sequence also needs to be cascaded. The output voltage of the first regulator needs to be up and stable before enabling the downstream regulator, otherwise startup overshoot can occur.
Even without being configured for cascaded operation, the user may prefer the cascaded sequence to prevent startup latch-up or race conditions. With the four independent enables provided, the user can program any power up sequence that the application requires. The enable pins can be controlled by a host processor, a programmable logic device, or a power supply sequencer IC. If the application requires a simpler implementation of the cascaded sequence startup, a single enable signal can be used to start the first regulator in the sequence. When the first regulator is near or in regulation, its output is used to enable the next regulator in the sequence. See Figure 22. Note that there is a time delay from when the enable signal is asserted, until when the soft start ramp begins. For Buck Converter 1, the delay is typically 1.0 ms. For Buck Converter 2 and 3, the delay is typically 160 s. When sequencing the regulators on, one parameter that must be considered is the leakage specification. Buck Converters 2 and 3 exhibit 400 A of leakage current between VIN and the switch node. This results in the output voltage floating up if the load impedance is high. In cases where the output voltage is floating, it is recommended adding a 1.0 KOhm resistor between the output and ground.
R3 R4 R5 R6
ENABLE
EN1
VOUT1
R1 R2
EN2
VOUT2
EN3
VOUT3
LDO_EN LDO
EN1
PGOOD VOUT1 VOUT2 VOUT3 LDO
1ms
3.2ms 3.2ms
3.2ms 0.5ms 0.1ms
t
Figure 22. 34700 Cascade Sequence
SHUTDOWN SEQUENCE
The shutdown sequence is controlled by the enable pins. By pulling the ENABLE pin low or letting it float, the corresponding regulator is disabled. If the application is being controlled by the host processor or programmable logic device, the regulators can be shutdown in any order. Most power supply sequencer ICs shutdown the regulators in the reverse order of their startup. The first regulator that is turned on is the last regulator to be turned off. For the single ENABLE pin sequencer shown
in Figure 22, the shutdown order is the same as for startup; the first regulator that is turned on, is the first regulator turned off.
LAYOUT GUIDELINES
The layout of any switching regulator requires careful consideration. First, there are high di/dt signals present, and the traces carrying these signals need to be kept as short and as wide as possible to minimize the trace inductance, and therefore reduce the voltage spikes they can create. To do this an understanding of the major current carrying loops is
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FUNCTIONAL DEVICE OPERATION DESIGN AND COMPONENT GUIDELINES
important. See Figure 23. These loops, and their associated components, should be placed in such a way as to minimize the loop size to prevent coupling to other parts of the circuit. Also, the current carrying power traces and their associated return traces should run adjacent to one another, to minimize the amount of noise coupling. If sensitive traces must cross the current carrying traces, they should be made perpendicular to one another to reduce field interaction. Second, small signal components which connect to sensitive nodes need consideration. The critical small signal components are the ones associated with the feedback circuit. The high impedance input of the error amp is especially sensitive to noise, and the feedback and compensation components should be placed as far from the switch node, and as close to the input of the error amplifier as possible. Other critical small signal components include the bypass capacitors for VIN, VGREG, and VDDI. Locate the bypass capacitors as close to the pin as possible.
The use of a multi-layer printed circuit board is recommended. Dedicate one layer, usually the layer under the top layer, as a ground plane. Make all critical component ground connections with vias to this layer. Make sure that the power grounds, GND2 and GND3, are connected directly to the ground plane and not routed through the thermal pad or analog ground. Dedicate another layer as a power plane and split this plane into local areas for common voltage nets. The IC input supply (VIN) should be connected through an RC filter to the 9.0 to 18 V input supply, to prevent noise from Buck Regulator 1's power input (VIN1) from injecting switching noise into the analog circuitry. If possible, further isolation can be made by routing a dedicated trace for VIN, and a separate trace for VIN1. In order to effectively transfer heat from the top layer to the ground plane and other layers of the printed circuit board, thermal vias need to be used in the thermal pad design. It is recommended that 5 to 9 vias be spaced evenly and have a finished diameter of 0.3 mm.
VIN1
VIN2 and 3 Loop Curr ent HS ON HS SW2 and 3 Loop Current SD ON LS GND2 and 3 Loop Current LS ON Loop Curr ent HS ON
HS SW1 SD
BUCK CONVERTER 1
BUCK CONVERTER 2 and 3
Figure 23. Current Loops
COMPONENT SELECTION
Setting the Output Voltage For all the regulators, the feedback resistor divider sets the output voltage. See Figure 24 for the feedback and compensation components referred to in the equations. For the buck regulators, choose a value of about 20 K for the upper resistor, and calculate the lower resistor using the following equations:
For the LDO regulator choose a value of about 10 K for the lower resistor, and calculate the upper resistor using the following equations:
V RTOP = RBOT OUT - 1 V REF R VOUT = VREF TOP + 1 R BOT
where, VREF = 0.7 V Choose the closest standard resistance values, check the output voltage by using the equations above, and adjust the values if necessary. Setting the Enable for Cascade Sequencing For the cascaded startup sequence shown in Figure 22, the resistor divider sets the output voltage level where the
RBOT =
RTOP x VREF VOUT - VREF
R VOUT = VREF TOP + 1 R BOT
where, VREF = 0.7 V
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FUNCTIONAL DEVICE OPERATION DESIGN AND COMPONENT GUIDELINES
next the next regulator in the sequence will start or shutdown. For top resistors R1, R3, and R5, choose a value of 10 K, and calculate the value for the bottom resistors R2, R4, and R6, using the following equation:
RBOT =
0.78 x RTOP 0.95VOUT - 0.78
results in lower efficiency. A value of 0.3 to 0.4 for N represents a good trade off between efficiency, ripple, and load transient response. After calculating a value for the inductor, choose the closest standard value and then determine the ripple current and peak current using the following equations:
where, VOUT is the value calculated above using standard value resistors. Choose the closest standard resistance values and check the output voltage levels that enable and disable the regulator in sequence, using the following equations, and adjust if necessary:
I L =
(V
IN(MAX)
- VOUT ) I L 2
L
x
VOUT 1 x VIN(MAX) f SW
I PEAK = I OUT(MAX) +
R + RBOT VOUT ( EN ) = 0.78 TOP RBOT R + RBOT VOUT ( DISABLE ) = 0.61 TOP RBOT

The peak inductor current determines the required saturation current rating of the inductor. Choose an inductor with a saturation current rating that's large enough to compensate for circuit tolerances. The minimum acceptable margin for this purpose is at least 20% above the calculated rating. To minimize copper losses, choose an inductor with the lowest possible DCR. As a general rule of thumb, look for a DCR of approximately 5.0 mOhms per H of inductance. Output Capacitor The output capacitor is required to minimize the voltage overshoot and undershoot in response to load transients, and to reduce the ripple present at the output of a buck regulator. The same holds true for the linear regulator. For the LDO, a 10 F, low ESR capacitor is required as the output capacitor. Other values may result in instability. Make sure the capacitor has good temperature characteristics, and a suitable voltage rating. As a general rule, choose ceramic capacitors with a X5R, or X7R dielectric and a voltage rating of 1.5 to 2 times the output voltage, but check with the manufacturer for detailed information. For the buck converters, large transient load overshoots are caused by insufficient capacitance, and large voltage ripple is caused by insufficient capacitance, as well as high equivalent series resistance (ESR) in the capacitor. To meet the application requirements, the output capacitor must be specified with ample capacitance and low ESR. To deal with overshoot, where the output voltage overshoots its regulated value when a full load is removed from the output, the output capacitor must be large enough to prevent the energy stored in the inductor from causing the voltage to spike above the specified maximum output voltage. The amount of capacitance required can be estimated using the following equation:
These equations should give an enable of ~95% of VOUT, and a disable of ~75% of VOUT. Catch Diode An external catch diode is required for Buck Converter 1 to provide a return path for the inductor current when the high side switch is off. The catch diode should be located close to the 34700 and connected using short, wide traces. See the Layout Guidelines for more details. It is recommended to use a Schottky diode, due to their low forward voltage drop and fast switching speed. This provides the best efficiency and performance, and is especially true when the output voltage is less than 5.0 V. Choose a Schottky with a 2.0 to 3.0 A average output current rating and a reverse voltage specified for 30 V. Inductor The output inductor is sized to meet the output voltage ripple requirements, and to minimize the load transient response time. For continuous conduction mode (CCM) operation, where the inductor does not fully discharge during the switch off time, and assuming an ideal switch and catch diode, the following equation is used:
L = (VIN(MAX) - VOUT )x
VOUT 1 1 x x VIN(MAX) f SW N x I OUT ( MAX )
where, fSW is the switching frequency and N is the ripple current to output current ratio. A high ripple current to output current ratio gives improved load transient response, but also increases output ripple, and
C OUT
L(I PEAK ) = (V + VOUT )2 - VOUT 2
2
where, V is the maximum output voltage overshoot.
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FUNCTIONAL DEVICE OPERATION DESIGN AND COMPONENT GUIDELINES
Allow a 20% capacitance tolerance and choose the closest standard value. The ESR of the output capacitor usually dominates the output voltage ripple. The maximum ESR can be calculated using the equation:
C ESR =
VRIPPLE I L
which is referenced to the switch node (SW) or the source of the high side MOSFET. The bootstrap capacitor is charged every cycle, when the low side MOSFET or the catch diode conducts, to a voltage of about VGREG. To turn the high side switch on, the bootstrap capacitor needs to be large enough to charge the gate-source capacitance of the N-MOSFET without a significant drop in voltage. For the 34700 the bootstrap capacitor should be 0.1 F. Compensation The voltage mode buck converters used in the 34700 require a Type III compensation network as shown in Figure 24. The Type III network utilizes two zeroes to give a phase boost of 180. This phase boost is necessary to counteract the double pole of the output LC filter.
where, VRIPPLE is the specified ripple voltage allowed. Input Capacitor Generally, a mix of bypass capacitors is used for the input supply. Use a small ceramic capacitor for high frequency decoupling, and bulk capacitors to supply the surge of current required each time the high side MOSFET turns on. Place the small ceramic capacitor close to the power input pins. For reliable operation, select the bulk input capacitors with voltage and RMS ripple current ratings above the maximum input voltage, and the largest RMS current required by the application. As a general guideline, the capacitor's voltage rating should be around 1.5 times the maximum input voltage, but the manufacturer's de-rating information should be followed. The RMS ripple current rating that the bulk input capacitors require can be estimated by the following equation:
C2
Cff
Rff
RTOP CCOMP
COM P
RCOMP
FB
EA
RBOT VREF 34700
+
I IN ( RMS ) = I OUT D - D 2
where D = VOUT/VIN. The worst case occurs when VIN = 2 x VOUT, yielding a worst case ripple current of IIN(RMS) = IOUT/2. The bulk input capacitance required for a buck converter depends on the impedance of the input supply. For common laboratory supplies, 10 to 20 F of capacitance per ampere of input ripple current is usually sufficient. Use this general guideline as a starting point and adjust the input capacitance based on actual test results. Tantalum capacitors can be used as input capacitors, but proper de-rating must be used or they can fail "short" and present a fire hazard. Ceramic capacitors and aluminum electrolytic capacitors don't have this failure mechanism, making them a preferred choice. However, ceramic capacitors can exhibit piezo effect and emit an audible buzz. Polymer capacitors do not have this audible noise problem, but they can also fail "short". However, polymer capacitors are much more robust than tantalums, and therefore are suitable as input capacitors. Consult the manufacturer for more information on the use and de-rating of capacitors. Bootstrap Capacitor The external bootstrap capacitor is part of a charge pump circuit which is used to drive the gate of the high side NMOSFET. This capacitor develops a floating voltage supply
Figure 24. Type III Compensation Network The closed loop transfer function is comprised of the modulator, the filter, and the compensation transfer functions. Before we can determine the compensation we need to first calculate the gains and break frequencies of the modulator and filter.
G MOD =
D MAX x VIN VRAMP
where, GMOD is the modulator gain, and DMAX and VRAMP are given in the electrical table.
f LC =
1 2 L x C
where, fLC is the location of the LC filter double pole.
f ESR =
1 2 x C x ESR
where, fESR is the location of the ESR zero, and ESR is the equivalent series resistance of the output capacitors. As shown in Figure 24, the compensation network consists of the error amplifier (internal to the 34700), and the
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FUNCTIONAL DEVICE OPERATION DESIGN AND COMPONENT GUIDELINES
external resistors and capacitors. If designed properly, the compensation network will yield a closed loop transfer function with a high cross-over (0 dB) frequency, and adequate phase margin to be stable. Use the following steps to calculate the compensation components. 1. Using the value for RTOP and RBOT, selected in the Setting the Output Voltage section, calculate the value of RCOMP for the desired converter bandwidth, f0. Typically f0 is chosen to be 1/10th of the switching frequency.
frequency, making the calculated value of C2 very small. If this is the case, C2 may not be needed, saving a component and space.
C2 =
C COMP (2 x R COMP x CCOMP x f ESR ) - 1
R COMP =
VRAMP x R TOP x f 0 D MAX x VIN x f LC
4. Calculate the value of Rff and Cff, to place a zero (fZ2) at the LC double pole frequency, and a pole (fP2) at half the switching frequency.
This will set the high frequency gain of the error amplifier (RCOMP/RTOP), and shift the open loop gain up to give the desired bandwidth. 2. Using the value for RCOMP, calculate the value of CCOMP, to place a zero, to cancel one of the double poles. This zero (fZ1) is placed at a fraction of the LC double pole frequency.
R ff =
R TOP f SW 2 x f -1 LC 1 x R ff x f SW
C ff =
C COMP =
1 2 x R COMP x K LC x f LC
where, KLC is the fraction of the LC filter frequency = fZ1/fLC. Typical values for KLC are 0.2 to 0.7, but begin with 0.5. 3. Using the values of RCOMP and CCOMP, calculate the value of C2 to place a pole (fP1) at the ESR zero frequency. Note that if ceramic capacitors are used for the output capacitors, the ESR zero will be at a very high
Choose the closest standard value for the compensation components. Although precision components are not required, do not use poor quality components that have large tolerances over-temperature. As a double check, it is recommended to use a mathematical model to plot the closed loop response. Check that the closed loop gain is within the error amplifier's open loop gain, and there is enough phase margin, and make adjustments as necessary. A stable control loop has a gain crossing with close to -20dB/decade, and a phase margin of at least 45. The following equations describe the frequency response of the modulator, feedback compensation, and the closed loop.
G MOD (f) = H COMP (f) =
D MAX x VIN 1 + s(f) ESR C VRAMP 1 + s(f) (ESR + DCR ) C + s 2 (f) L C 1 + s(f) R COMP C COMP s(f) R TOP (C COMP + C 2 )
1 + s(f) (R TOP + R ff ) C ff C C 1 + s(f) R ff C ff 1 + s(f) R COMP COMP 2 C COMP + C 2
G CL (f) = G MOD (f) H COMP (f) where, s(f) = j 2 f
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FUNCTIONAL DEVICE OPERATION
A more intuitive representation of the mathematical model, is an asymptotic bode plot of the buck converter's gain versus frequency, as shown in Figure 25. Use of the previous steps should result in a compensation gain similar to the one shown in the bode plot. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at fP1 or fP2, whichever is greater, against the capabilities of the error amplifier. For reference, the equations for the compensation break frequencies are given.
f Z1 = f P1 =
1 2 x R COMP x C COMP 1 C x C2 2 x R COMP x COMP C COMP + C 2 1 2 x (R TOP + R ff )x C ff 1 2 x R ff x C ff
f Z2 = f P2 =
fZ1 fZ2 fP1
GAIN (dB)
fP2
ERROR AMP OPEN LOOP
0
HCOMP
GCL
GMOD
fLC
fESR
f0
FREQUENCY (LOG Hz)
Figure 25. Bode Plot of the Buck Converter
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APPLICATION EXAMPLE
VIN1
FB1
AGND
VDDI
COMP1
VOUT1
VOUT1 3.3V
C13 10F D1 B320A BST1 GND2 L2 4.7H SW2 VIN2 COMP2 FB2 EN1 EN2 EN3 EN_LDO FB3 COMP3 C17 .1F BST2 BST3 VIN3 C26 .1F C22 1000pF R11 5.6k R12 24k R14 20k C23 22pF C25 1F C18 1F SW3 SW1 LDO R15 2.87k C15 C16 10F 10F SW1 LDO_VIN LDO_FB GND3
C12 C11 10F 10F C14 .1F VIN1
PGOOD
VGREG
22
VIN 9 to 18V
R1 200 C5 2700pF R4 3.6k C7 1F R5 10k C6 1F R2 18k 4.7k R3 C4 22pF C3 560pF C1 22F C2 22F
34700
PGOOD
R6 4.7 C8 1F C10 1F C9 1F L1 4.7H VIN R16 10k L3 C27 4.7H 10F
R17 TBD
MC34700
C29 10F
VOUT_LDO 0.9V
APPLICATION EXAMPLE
Figure 26. 34700 Typical Application
R7 680 C19 560pF R10 15k R8 15.8k R9 6.19k C20 22pF C21 1000pF C24 R13 1200pF 150
VOUT2 2.5V
C28 10F
R18 TBD
VOUT3 1.25V
Analog Integrated Circuit Device Data Freescale Semiconductor
EN1 EN2 EN3 EN4
APPLICATION EXAMPLE BILL OF MATERIAL
BILL OF MATERIAL
Table 1. MC34700 Bill of Material
Item R1 R2 R3 R4 R5, R16 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 C1, C2 C3, C19 C4, C20, C23 C5 C6 - C10, C18, C25 C11-C13, C15, C16, C27 - C29 C14, C17, C26 C21, C22 C24 L1, L2, L3 D1 Qty 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 2 2 3 1 7 8 3 2 2 3 1 Part Designer 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 201/402/603 Metal or Thin Film Resistors 25V 1210/1206 MLCC Capacitors X5R/X7R 50V 0402/0603 MLCC Capacitors COG 50V 0402/0603 MLCC Capacitors COG 50V 0402/0603 MLCC Capacitors X5R/X7R 25V 0402/0603 MLCC Capacitors X5R/X7R 10V 1210/1206 MLCC Capacitors X5R/X7R 25V 0402/0603 MLCC Capacitors X5R/X7R 50V 0402/0603 MLCC Capacitors X5R/X7R 50V 0402/0603 MLCC Capacitors X5R/X7R 3A Shielded Inductor 2A, 30V Schottky Diode Value / Rating 200 18.0 k 4.70 k 3.60 k 10.0 k 4.7 680 15.8 k 6.19 k 15.0 k 5.6 k 24.0 k 150 20.0 k 2.87 k 22 F 560 pF 22 pF 2700 pF 1.0 F 10 F 0.1 F 1000 pF 1200 pF 4.7 H B230A Part Number / Manufacturer
Note:
Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer's responsibility to validate their application.
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APPLICATION EXAMPLE PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a "keyword" search using the 98AXXXXXXXX listed.
EP SUFFIX (Pb FREE) 32-PIN 98ASA10800D REVISION D
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Analog Integrated Circuit Device Data Freescale Semiconductor
APPLICATION EXAMPLE PACKAGE DIMENSIONS
EP SUFFIX (Pb FREE) 32-PIN 98ASA10800D REVISION D
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APPLICATION EXAMPLE PACKAGE DIMENSIONS
EP SUFFIX (Pb FREE) 32-PIN 98ASA10800D REVISION D
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Analog Integrated Circuit Device Data Freescale Semiconductor
INTERNAL REVISION HISTORY PACKAGE DIMENSIONS
INTERNAL REVISION HISTORY
REVISION 1.0 2.0 3.0 4.0 5.0 DATE 4/2008 4/2008 5/2008 6/2008 6/2009 DESCRIPTION OF CHANGES * * * * * * Initial release Changed the 98A package drawing from 98ARE10566D to 98ASA10800D Corrected error on MC34700 Simplified Application Diagram on page 1 Changed category from "Advance Information" to "Technical Data" Converted the datasheet to the PMMIC format Added waveforms
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FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2009. All rights reserved. MC34700 Rev. 5.0 10/2009

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